module coe_upgrade
	#(parameter length = 16)
	(
		input clk,
		input rst_n,
		input signed [length-1:0] IS,
		input signed [length-1:0] error_distance,
	
		output reg signed [length-1:0]	W
	);

wire signed	[2*length-1:0] mult_res;
Mult #(length) Mult_u0(.Mulr(IS), .Muld(error_distance), .result(mult_res));

wire signed [length-1:0] shift_res;
assign shift_res = {{8{mult_res[2*length-1]}}, mult_res[2*length-1-:8]};//步长选择1/256,左移8位,过拟合，使用16384，左移14位


reg signed [length-1:0] shift_res_r, W_pre;



always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		W <= 0;
		W_pre <= 0;
		shift_res_r <= 0;
	end 
	else begin		
		W_pre <= W;
		shift_res_r <= shift_res;
		W <= W_pre + shift_res_r;
	end 
end 

endmodule